Complex microelectronic components have several levels of semiconductor structures positioned above one another. Dielectric layers interposed between the levels insulate structures on one level from structures on an adjacent level. The structures are accordingly sandwiched between the dielectric layers. Structures on different levels may then be selectively coupled with conductive lines extending through the intermediate dielectric layers between the structures.
The dielectric layers between each level must be extremely thin to minimize the overall thickness of the microelectronic component. The dielectric layers must also be extremely flat to enable precise circuit patterns and structures to be formed in the layers using photolithography and photo pattern techniques. As the density of the structures within the microelectronic component increases, it is often necessary to accurately focus the critical dimensions of the photo patterns to within a tolerance of approximately 1 .mu.m. Focusing the photo patterns to such small tolerances, however, is difficult when the surface of the dielectric layer is not uniformly planar.
Current methods for flattening the surface of dielectric layers or other substrates include chemical mechanical planarization (CMP) processes which chemically and/or mechanically remove material from the dielectric layer. One problem with current CMP processes is that they are extremely time consuming and therefore increase the overall time required to manufacture the microelectronic components. Another problem with current CMP processes is that a trial-and-error end-pointing technique is used to determine when a sufficient amount of material has been removed from the dielectric layer. The trial-and-error technique is time consuming and may not accurately determine when the proper amount of material has been removed. If an insufficient amount of material is removed, the layer may be too thick and/or may not be sufficiently flat. If an excessive amount of material is removed, the structures beneath the dielectric layer may be damaged.
A further problem with current CMP techniques is that the planarizing rate may vary across the surface of the dielectric, reducing the uniformity of the planarized surface and therefore the ability to uniformly focus photo patterns on the surface to small tolerances. As the microelectronic components are made smaller, the photo patterns must be focused to smaller tolerances and the effects of surface non-planarity accordingly increase.
Yet a further problem with current CMP processes is that the processes produce debris, such as particulates removed from the dielectric material and particulates incidentally removed from the planarizing device as it abrades the dielectric material. The particulates may contaminate or otherwise damage the microelectronic component.
CMP processes are further disadvantageous because they require post-processing steps, such as rapid temperature processing (RTP) and densification to purify and consolidate the planarized layer. The steps are not only time consuming, but also heat the microelectronic component. Because each component has a limited thermal budget and can therefore withstand only a limited amount of heat before failing, the post-processing steps increase the likelihood that the component may fail and limit the amount of heat to which the component may be subjected during other phases of production.
Another problem with current CMP processes is that they require the dielectric layers to be formed on the microelectronic component before the layers are planarized. Current methods for forming the dielectric layers include depositing the layers upon the structures of the microelectronic component using a variety of deposition techniques. However, as the structures are made increasingly non-uniform and the components themselves are made smaller, the dielectric layers may not conform well to the structures. As a result, the layers may break or become discontinuous, allowing structures on different levels of the component to inadvertently come into electrical contact with each other. Thus, current methods for forming the dielectric layers are inadequate.
Current methods for flattening the surface of a dielectric layer also include subjecting the dielectric layer to high pressure, as disclosed by U.S. Pat. No. 5,434,107 to Paranjpe. Paranjpe discloses filling the submicron spaces of a semiconductor wafer with an interlevel dielectric material to locally planarize the wafer. The wafer is then coated with a film of deformable material, such as a low melting point metal or alloy, spun on glass, a suitable resin or a reflowable glass. The deformable film is squeezed under high pressure to form a flat surface, and then cured by raising the temperature of the film. The film may be squeezed by either pressing the film against a flat plate or by disposing a high pressure fluid between a flat plate and the film. Where the film is compressed by a high pressure fluid, the fluid is pressurized between a movable chuck which supports the wafer and dielectric layer, and a movable piston.
One disadvantage with the high pressure method discussed above is that it requires that both an interlevel dielectric material and a deformable film be placed on the semiconductor wafer to form a planar surface thereon. The two-step process increases the amount of time and material cost required to produce a planar dielectric layer. A further disadvantage is that the apparatus discussed above incorporates a plurality of moving parts which may be subject to wear and possibly failure due to the high pressure conditions under which they operate.